Snr ASIC Design Engineer

 Deconstruct Requirements & Design: Evaluate system requirements to

architect and implement robust, high-performance digital logic and IP

blocks.

 Front-End Flow Ownership: Drive designs through the front-end ASIC

flow, including RTL coding, linting, clock domain crossing (CDC)

analysis, and initial synthesis.

 Verification Collaboration: Write block-level self-checking testbenches

and collaborate with the verification team to expand top-level UVM

environments.

 Architectural Influence: Propose innovative changes to chip

architecture, power-saving strategies, and team methodologies.

 Cross-Functional Sparring: Act as a core technical sparring partner to a

diverse engineering team, continuously pushing for better ways of doing

things.

To thrive in this role, you should bring:

 Experience: 8+ years as a digital design engineer within an R&D or fabless ASIC environment, with a proven track record of successful silicon tape-outs/deliveries.

 RTL & Architecture: Deep fundamental knowledge of digital design, IP development, and RTL coding using VHDL and/or Verilog.

 EDA Tools & Flow: Strong experience with standard ASIC front-end EDA tools, processor/bus-system architectures (e.g., AMBA AXI/AHB protocols), and synthesis.

 Timing & Constraints: Solid understanding of static timing analysis (STA) constraints and timing closure methodologies.

 Mixed-Signal Familiarity: Understanding of analog/mixed-signal chips or IP (e.g., ADC/DAC interfaces, PLLs).

 Automation & Tools: Proficiency in scripting to automate design workflows (Python, Tcl, Shell) and version control (Git).

 Communication: Strong communication and collaboration skills.